A NAND memory array typically consists of several strings of memory cells connected in series. Each string of memory cells typically includes a source select transistor SST to selectively connect the string to a common source line SL, and a drain select transistor DST to selectively connect the string to a bitline BL<i>.
For example, FIG. 2 shows a simple NAND memory array that consists of four strings with each string having four memory cells connected in series. The four strings are connected through their respective drain select transistors DSTs to the two bitlines, BL<0> and BL<1>, and through their respective source select transistors SSTs to the common source line SL. The two strings in the upper part share the drain select transistor gate line GDST and the source select transistor gate line GSST, as well as the memory cell gate lines, which are called wordlines WL. The GDST is a line that is connected to a gate of the drain selector transistor DST, and the GSST is a line that is connected to a gate of the source select transistor SST.
The two strings in the lower part also share the same structure. The strings that share the same GDST and GSST lines build a block, and accordingly, there are two blocks in the memory array shown in FIG. 2.
Further, as shown in FIG. 2 the strings in the upper left corner and the lower left corner share the bitline BL<0> whereas the strings in the upper right corner and the lower right corner share the bitline BL<1>. The strings that share a common bitline can be referred to as being stacked on each other.
A block in a NAND memory array typically includes a couple of GDSTs and GSSTs and a total number of wordlines WLs enclosed between them, while this total number of WLs represents the total number of physical cells in a string. This number is typically 32 but may be higher.
In order to perform various operations on a NAND memory array, for example, a read/program or an erase operation, a single memory cell to which the desired operation is directed can be selected among other memory cells in the memory array. A row driver circuit is the circuit used in selecting a single target cell in the memory array. In order to select a target cell in the memory array, a bitline that the target cell is connected to, a block in which the target cell is placed, and a wordline that the target cell is connected to can be selected. By selecting these three characteristics with which each memory cell is associated—the bitline, the block and the wordline—a memory cell in the matrix array can be singled out. In other words, each memory cell in the matrix array has a unique combination of these three characteristics—the bitline, the block and the wordline.
A target bitline, a target block and a target wordline can be selected by performing the following steps:                (i) select a bitline by applying an appropriate voltage BLSEL on the desired bitline while applying a different voltage BLUNSEL on the other bitlines;        (ii) select a block by activating the related drain select transistor gate line GDST and the related source select transistor gate line GSST. This lets the voltage applied on the selected bitline pass through the drain select transistor DST to the string as well as lets the common source line SL connect to the string through the source select transistor SST; and        (iii) select a wordline by biasing it at a predetermined voltage VXSEL while biasing the remaining unselected wordlines at a voltage that would be suitable to turn on the related connected cells in order to bias the drain of the selected memory cell to the BLSEL voltage, by making a short circuit between the node and the bitline. This voltage that is used for unselected wordlines is referred to as VXPASS.        
A row driver is involved in the third step above and used to drive appropriate voltages on wordlines in a block with which the row driver is associated.
Furthermore, depending on the type of operation that a target cell is subjected to—for example, a read, program, or erase operation—different voltages are driven on each wordline WL, drain select transistor gate line GDST, and source select transistor gate line GSST.
Presently, there are several row driver circuits available in the art, which aim to drive appropriate voltages on WLs, GDST lines and GSST lines during various operations. An exemplary architectural scheme of the state-of-art row driver is shown in FIG. 3, which includes a boosting capacitor and a level shifter. The boosting capacitor can be used to allow high voltages to pass onto the wordlines, and the level shifter can be used to transform the power in the input stage of the row driver.
Further, in designing a circuit for a row driver, the size can be a factor to consider as it is generally desirable for a flash memory to be as small as possible. The height of a row driver circuit is typically fixed by technological restrictions or requirements such as the height of the strings in the matrix array. On the other hand, certain characteristics can be altered such as the planar area that is occupied by the row driver circuit. Accordingly, the planar area can be minimized so as to make the size of the final circuit as integrated on silicon as small as possible.
One way to minimize the planar area that would be occupied by the row driver circuit is to use a minimum number of transistors. Therefore, it is generally desirable to design a row driver circuit that would not only have a fast and stable performance but also achieve such performance level with a minimum number of transistors.
FIG. 3 shows exemplary circuit architecture for the state-of-art row driver including a boosting capacitor and an isolating pass transistor. M12, M9, M6, M1<i>, M2, M3, M4 and M5 are ultra high voltage n-type transistors. M10 and M11 are ultra high voltage p-type transistors. C1 is a boosting capacitor of ultra high voltage type that is connected to the driving circuit, node B, through pass transistor M6 which is used to isolate C1 during the boosting stage. M12, M9, M11 and M10 form a level shifter circuit, which is used to shift the voltage level Vpwr on input line SELb to a high voltage level HVV on the output node, which can be either (A) or (B), wherein HVV is the high voltage level of line HVVL. A first switch, not shown and which is not part of the invention, drives the HVVL line at two different voltages: a low voltage equal to Vpwr level, and a high voltage, equal to HVV. On the other hand, a second switch, which is not shown in the figure, drives line HVCL connected to the gate of M6 to a low voltage level equal to Vpwr or to a high voltage level equal to HVC, wherein the high voltage level HVC can be higher or equal to the voltage level HVV. M6 is a decoupling switch that can disconnect C1 and the circuit on its right side from node B.
In this embodiment, the level shifter circuit is enabled when the voltage level of line HVVL is at Vpwr. This helps the p-type transistors M10 and M11 to be sized with the minimal length. As explained above, the level shifter circuit is formed by M9, M10, M11 and M12, wherein M9 and M12 are n-type transistors and M10 and M11 are p-type transistors. The maximum gate-source voltage Vgs of the n-type transistors M9 and M12 is Vpwr. On the other hand, the maximum Vgs voltage of the p-type transistors M10 and M11 is “HVVL-V(A)” or “HVVL-V(B).” For example, the maximum Vgs of the p-type transistors M10 and M11 is HVVL, which occurs when node A or B is grounded. Thus, when HVVL is at Vpwr, the “voltage strength” for n-type and p-type transistors is the same. Further to ensure that the level shifter can flip in response to SELb transition, the size of the p-type transistors M10 and M11 may be drawn to about the same size as that of the n-type transistors M9 and M12. Thus, letting the level shifter circuit be enabled when HVVL is at Vpwr helps to minimize the size of the transistors M9˜M12.
Instead, if the level shifter is made to be enabled when HVVL is at a higher voltage than Vpwr, i.e., HVV, “the voltage strength” of the p-type transistors, which forms a pull-up section, becomes greater than that of the n-type transistors, which forms a pull-down section. For example in FIG. 3, the pull-up section M10-M11 would become too strong with respect to the pull-down section M9-M12, and as a consequence the shifting of the input signal SELb may not be successfully translated into the shifting of voltage levels on nodes A and B. In this case, to restore the balance between the pull-up section M10-M11 and the pull-down section M9-M12, the length L of the p-type transistors or the width W of the n-type transistors shall be incremented, which results in increasing the area on silicon that would be occupied by the level shifter circuit.
In the embodiment depicted in FIG. 3, SELb is a logical signal whose input can range from 0V to Vpwr. Signal SELb works as a control signal of the whole row driver circuit: if the row driver is in an unselected block, SELb is at Vpwr, and if the row driver is in a selected block, SELb is at 0V. In other words, if SELb is at Vpwr, the row driver is configured to not drive any voltages onto wordlines WLs, and if SELb is at 0V, the row driver is configured to drive appropriate voltages onto wordlines WLs.
As said, voltage levels HVV and HVC represent high voltage levels, each being greater than Vpwr. Lines HVVL and HVCL as shown in FIG. 3 take as input a voltage selectable in a range between Vpwr to HVV, provided that HVV is less than HVC. VX<i> represent voltages, each of which is to be applied to either selected or unselected wordlines. GSELD and GSELS represent voltages, each of which is to be applied to lines GDST and GSST in the associated memory block. Signal ERASE is a logical signal whose input can range from 0V to Vpwr. ERASE is at a logical high state when the voltage level of ERASE is at Vpwr, and at a logical low state when the voltage level of ERASE is at 0V. ERASE is at the logical high state when an erase operation is on-going and remains otherwise at the logical low state.
GBOOST is a boosting line that outputs whichever is higher between voltage VSEL and voltage VPASS during pulse read or pulse program stages in a read/program operation. GBOOST helps to boost node K to elevate towards a voltage that is higher than HVV during the pulse read or pulse program stages. GBOOST remains at ground voltage in other stages of a read/program operation. GBOOST remains at ground voltage during an erase operation as well.
HVVL, HVCL, VX<i>, GSELD, GSELS and GBOOST lines can be controlled by a uC unit inside the NAND memory, which can control the whole system of a NAND memory. An exemplary uC unit is shown in block 5 in FIG. 1.
Voltages on different lines can evolve as the row driver goes through different stages of an operation. FIG. 5b shows an exemplary waveform of voltages representing how different voltages evolve during different stages of a read/program operation. FIG. 5e shows an exemplary waveform of voltages representing how different voltages evolve during different stages of an erase operation. The following paragraphs discuss these evolutions in more detail.
An exemplary operation of the row driver circuit is explained when the block is unselected. That the block is unselected means that no operation is to be performed on the corresponding wordlines of the block. This condition can be achieved by the row driver circuit failing to drive voltages onto the corresponding wordlines. In other words, the row driver circuit may leave the voltages on each of the corresponding wordlines floating.
When the block is unselected, a control signal of the row driver SELb is set at Vpwr. Then, M12 is turned off, and M9 is turned on. Until the level shifter has completely commuted, lines HVVL and HVCL are kept biased at Vpwr. With SELb stable at Vpwr level, node B is tied to ground, A is tied to HVVL, which is kept at Vpwr, and node K is kept at ground via M6, since GBOOST is at 0V during the input stage. Then, M1<i> is turned off resulting in wordlines WL<i> left floating.
Further, M4 and M2 are turned off at this point, and M5 and M3 have their gates connected to SELb which is at Vpwr. At this point, the two following scenarios are possible:                (1) If ERASE is at 0V, GDST and GSST lines are kept at ground, erasing the DST and SST cells; or        (2) If ERASE is at Vpwr, GDST and GSST are left floating, not erasing the DST and SST cells.        
Once the level shifter has commuted, line HVVL can be raised to high voltage HVV from Vpwr, and line HVCL can be raised to high voltage HVC from Vpwr, while node K remains at ground.
An operation of the row driver circuit is explained when the block is selected for a read/program operation. An exemplary waveform of voltage levels and transistor states during this operation is shown in FIG. 5b. When the corresponding block is selected, SELb takes an input voltage at 0V. Then, node A is tied to ground via M12, M9 is left floating, and node B rises to the voltage level of line HVVL, which is still kept at Vpwr voltage. This turns on the level shifter circuit. During this input stage of a read or program operation, GBOOST line is kept at ground until the level shifter has commuted, and node K is boosted so as to be ready for the pulse program or pulse read stages.
After the level shifter has commuted with node B being pulled up to line HVVL, which is still kept at Vpwr, line HVVL can rise from Vpwr to the high voltage level at HVV. In other words, only after the level shifter has commuted, line HVVL can rise to the high voltage HVV, which in turn can charge node K to the high voltage, provided that the high voltage HVV is lower than the high voltage HVC reduced by the threshold voltage of transistor M6. That is, node K is generally charged to the lower of (1) the high voltage HVV, and (2) the high voltage HVC reduced by the threshold voltage of transistor M6. For example, when HVC>HVV+threshold voltage of transistor M6, node K is charged to HVV voltage, as shown in the k-node pre-charge stage in FIG. 5b. 
After node K is elevated to the high voltage HVV, line HVCL is driven down from the high voltage level HVC to Vpwr. This can turn off transistor M6 and, accordingly, can isolate node K from the level shifter circuit. GBOOST line is then activated, which consequently can boost up the node K. Then, node K can turn on transistors M1<63:0> in order to pass voltages VSEL and VPASS from VX<i> lines onto wordlines WLs.
An operation of the row driver circuit is hereby explained when the block is selected for an erase operation. An exemplary waveform of voltage levels and transistor states during this erase operation is illustrated in FIG. 5e. ERASE signal is set at Vpwr. A successful erase operation means biasing the associated wordlines WLs at 0V. This can be achieved by keeping the line HVVL at Vpwr and the line HVCL at the voltage level that would be sufficient to short nodes B and K, wherein both nodes are to be shorted at the voltage Vpwr. Then, Vx<i> lines can be biased at ground, and thus worldliness WLs can be biased at ground through transistors M1<63:0>. During the erase operation, GDST and GSST lines are left floating. M5 and M3 are turned off since they have their gate voltages at ground potential. M4 and M2 are turned on since they have their gate voltages at Vpwr. By biasing GSELD and GSELS lines at Vpwr voltage, GDST and GSST lines can charge to the voltage that equals Vpwr reduced by the threshold voltage of M4 and M2. From this point onwards, lines GDST and GSST can be raised due to the coupling effects of the array well.
However, this state-of-art row driver circuit can be subject to several limitations. First, as remarked earlier, it is generally desirable to design a row driver circuit with a minimal planar area. One typical way to minimize the area occupied by the row driver circuit is to use minimally-sized transistors.
As explained above, the size of the transistors in the row driver circuit can be minimized by keeping the voltage line HVVL at Vpwr when input signal SELb is being shifted by the level shifter, the level shifter being the circuit consisted of transistors M11, M10, M9 and M12. For example, if line HVVL is not kept at Vpwr, the pull-up section M10-M11 would be too strong with respect to the pull-down section M9-M12, and as a consequence the shifting of the input signal SELb may not be successfully translated into the shifting of voltage levels on nodes A and B.
Another limitation to this state-of-art row driver is that capacitor C1 needs to be connected to node B when the level shifter is commuting (i.e. when the SELb is changing state) and line HVVL is evolving to HVV voltage, in order for a stable performance of the level shifter circuit. Without this connection of C1 to node B, the level shifter circuit can enter an undetermined state that can ultimately compromise the correct behaviour of the row driver circuit as a whole.
For example, if capacitor C1 is connected to node B, capacitor C1 starts to charge as soon as node B starts to rise from Vpwr to high voltage HVV as line HVVL starts to rise from Vpwr to high voltage HVV. With C1 connected to node B during the input stage, and SELb set at 0V (corresponding block is selected), node A becomes tied to ground, and node B is pulled up to line HVVL, which is at Vpwr. Then, line HVVL starts to rise from Vpwr to high voltage HVV. Node B follows the rise, and provided that line HVCL is sufficiently high to turn on transistor M6 (i.e. voltage HVC>HVV), C1 starts to charge as a result of the capacitive discharge from node B.
If, however, C1 is not connected to node B during the initial phase, the level shifter can enter the above-mentioned undetermined state. C1 can be disconnected during the initial phase by keeping line HVCL at Vpwr, which results in transistor M6 being turned off after voltage on node K reaches Vpwr reduced by the threshold voltage of M6. Then, capacitor C1 can remain disconnected from node B until line HVVL reaches its steady state at the high voltage HVV. When this occurs, the level shifter can enter the above-mentioned undetermined state, specifically due to line HVCL reaching its steady state at the high voltage HVC, thereby turning on transistor M6. This undetermined state is hereby explained in more detail, and an exemplary waveform of voltage levels of node B and node K showing this undetermined state is in FIG. 5d. 
If capacitor C1 is disconnected from node B during the initial phase by maintaining line HVCL at Vpwr potential until line HVVL has commuted to its high voltage level HVV, M6 remains turned off. Once line HVVL has commuted to the high voltage, line HVCL is driven to high voltage HVC, and then capacitor C1 and node B are connected through transistor M6 that has been turned on by line HVCL. However, such abrupt connection of C1 to node B can be dangerous, since C1 is charged at the low voltage level Vpwr reduced by threshold voltage of M6 until line HVCL is turned on, little parasitic capacitance of node B can be rapidly discharged as soon as line HVCL is turned on, because of the charge sharing between node B and the big capacitor C1 on node K. This capacitive discharge may result in shorting node B and node K to each other at a low voltage level that can become at near ground potential. Then, it can be difficult to predict the voltages on node B and node K, and thereby node B and node K will enter the undetermined state, as shown in FIG. 5d. 
In this undetermined condition, line HVVL in the level shifter circuit is still kept at the high voltage level HVV, which results in a too strong pull-up section, M10-M11, and a too weak pull-down section, M12-M9, in the level shifter. With this unbalanced pull-up and pull-down sections, the level shifter may fail in recovering the correct voltage levels on node B and node K. This failure of the level shifter circuit may lead to failure of the row driver circuit as a whole, being unable to bias the associated matrix array correctly. Further, when this occurs, there can be a huge current consumption from line HVVL to ground. Then, the voltage level of line HVVL may start to drop, and as a consequence the whole circuitry connected to line HVVL may suffer. This whole phenomenon is referred to as the above-mentioned undetermined state to which the state-of-art row driver can enter when line HVVL is left reaching its high voltage level at HVV before line HVCL reaches its high voltage level at HVC. In order to prevent such condition occurring in the state-of-art row driver, it is necessary for C1 to be connected to node B during the commutation of the level shifter circuit.
On the other hand, the need of maintaining C1 connected to node B during the initial commuting phase of the level shifter can result in the following inefficiencies with respect to the performances of the state-of-art row driver circuit.                (1) First, a delay may be unavoidable for node B to complete its voltage commutation, and hence the time needed for the row driver to turn on may be slow. That is because the capacitive couplings between node B and capacitor C1 can delay the commutation of node B. For example, the transition of line HVVL from Vpwr to HVV needs to be sufficiently slow so as to enable the voltage on node K to follow the voltage on node B through transistor M6. If this condition is not met, the charge of node K will likely suffer a delay with respect to the charge of node B, and this asymmetry could lead to the undetermined state again. As a result, if the commutation of line HVVL and node B is slowed down, the commutation of node K is slowed down as well, which delays the charging of capacitor 1 and thereby slows the turning-on process of the row driver circuit as a whole.        (2) Second, the condition that line HVCL reach the high voltage level HVC before line HVVL reaches its high voltage level HVV may be required to avoid an undesirable operation of the row driver circuit, i.e., entering into the above-mentioned undetermined state. As explained above with FIG. 5d, the voltage levels on node B and node K become unstable when the condition is not met. This is a restriction in terms of the high voltage management, especially during the power-on phase when all the voltages are evolving to their steady state values.        
In sum, the state-of-art row driver is subject to several limitations, which may in turn make the row driver circuit as a whole inefficient, especially with respect to the high voltage management, the risk associated with the level shifter circuit of entering the undetermined state for failing to prepare the high voltage state HVC before HVVL reaches its high voltage state HVV during the initial commuting phase, and the delay associated with the commutation of the level shifter circuit, which is caused by the capacitive couplings between C1 and node B during the commutation of the level shifter circuit during the initial commuting phase.